Difference between revisions of "GSR linecard memory locations"
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| + | ==Engine 0 and Engine 1 LineCard memory locations== | ||
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| + | [[image:gsr_engine0_engine1_linecard_memory_locations.jpg|gsr engine 0 and engine 1 linecard memory locations]] | ||
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| + | '''1 - Route memory DIMM1'''<br/> | ||
| + | '''2 - Route Memory DIMM0'''<br/> | ||
| + | '''3 - Packet memory RX DIMM0 (receive packet memory)'''<br/> | ||
| + | '''4 - Packet memory RX DIMM1 (receive packet memory)'''<br/> | ||
| + | '''5 - Packet memory TX DIMM0 (transmit packet memory)'''<br/> | ||
| + | '''6 - Packet memory TX DIMM1 (transmit packet memory)'''<br/> | ||
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==Engine 2 LineCard memory locations== | ==Engine 2 LineCard memory locations== | ||
[[image:gsr_engine2_linecard_memory_locations.jpg|gsr engine 2 linecard memory locations]] | [[image:gsr_engine2_linecard_memory_locations.jpg|gsr engine 2 linecard memory locations]] | ||
| − | 1 - Route memory DIMM1<br/> | + | '''1 - Route memory DIMM1'''<br/> |
| − | 2 - Route Memory DIMM0<br/> | + | '''2 - Route Memory DIMM0'''<br/> |
| − | 3 - Packet memory TX DIMM0<br/> | + | '''3 - Packet memory TX DIMM0 (transmit packet memory)'''<br/> |
| − | 4 - Packet memory TX DIMM1<br/> | + | '''4 - Packet memory TX DIMM1 (transmit packet memory)'''<br/> |
| − | 5 - Packet memory RX DIMM1<br/> | + | '''5 - Packet memory RX DIMM1 (receive packet memory)'''<br/> |
| − | 6 - Packet memory RX DIMM0<br/> | + | '''6 - Packet memory RX DIMM0 (receive packet memory)'''<br/> |
| − | 7 - TLU DIMM (not user serviceable)<br/> | + | '''7 - TLU DIMM (not user serviceable/configurable)'''<br/> |
| − | 8 - PLU DIMM (not user serviceable)<br/> | + | '''8 - PLU DIMM (not user serviceable/configurable)'''<br/> |
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| + | ==ISE LineCard memory locations== | ||
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| + | [[image:gsr_ise_linecard_memory_locations.jpg|gsr engine 2 linecard memory locations]] | ||
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| + | '''1 - Route memory SODIMM0'''<br/> | ||
| + | '''2 - Route Memory SODIMM1'''<br/> | ||
| + | '''3 - Four Packet memory SODIMM sockets (not field serviceable)'''<br/> | ||
| + | '''4 - Four TLU/PLU memory SODIMM sockets (not field serviceable)'''<br/> | ||
Latest revision as of 16:55, 12 March 2009
Engine 0 and Engine 1 LineCard memory locations
1 - Route memory DIMM1
2 - Route Memory DIMM0
3 - Packet memory RX DIMM0 (receive packet memory)
4 - Packet memory RX DIMM1 (receive packet memory)
5 - Packet memory TX DIMM0 (transmit packet memory)
6 - Packet memory TX DIMM1 (transmit packet memory)
Engine 2 LineCard memory locations
1 - Route memory DIMM1
2 - Route Memory DIMM0
3 - Packet memory TX DIMM0 (transmit packet memory)
4 - Packet memory TX DIMM1 (transmit packet memory)
5 - Packet memory RX DIMM1 (receive packet memory)
6 - Packet memory RX DIMM0 (receive packet memory)
7 - TLU DIMM (not user serviceable/configurable)
8 - PLU DIMM (not user serviceable/configurable)
ISE LineCard memory locations
1 - Route memory SODIMM0
2 - Route Memory SODIMM1
3 - Four Packet memory SODIMM sockets (not field serviceable)
4 - Four TLU/PLU memory SODIMM sockets (not field serviceable)
